Silicon photonics technology [1] provides one of the most promising solutions to the problem of what is to replace short-range metal interconnects as the requirements of chip-to-chip and board-to-board communication increase [2–4]. Some of the best silicon photonic optoelectronic (OE) modulators [5] reported in academia and industry are plasma dispersion effect (PDE) accumulation modulators [6–9] fabricated on an SOI substrate. Waveguides fabricated on SOI [10–12] benefit from the high refractive index difference (Δn=2.1) [13] between crystalline-Si (c-Si) and the buried oxide (BOX, SiO₂), which facilitates very high mode confinement in sub-micron waveguides [14], maximizing the light-matter interaction between the guided mode and free carriers for PDE phase change modulation. However, this high refractive index difference leads to high scattering induced optical loss as a consequence of fabrication induced sidewall roughness (and the associated refractive index variation), as loss scales proportionally to (Δn)³ [13,15]. Waveguide sidewall roughness is therefore a major source of optical loss [16]. A proposed solution to reduce sidewall roughness is to use local-oxidation-of-silicon (LOCOS) and tetramethylammonium hydroxide (TMAH) anisotropic wet etching of waveguides aligned to the (111) crystal plane of Si to produce atomically flat waveguide sidewalls [8,17,18].

Horizontal gate oxide accumulation modulators usually rely on either partially amorphous-Si (a-Si) [19] or polycrystalline-Si (poly-Si) [7] waveguides, which suffer from grain boundary induced optical loss, as well as non-optimal electrical characteristics compared to c-Si. A vertical gate-oxide accumulation modulator with fully c-Si slot waveguides has been demonstrated [9], although this requires a complex fabrication process to recover the crystal structure of deposited a-Si [20,21]. A high-speed, fully-crystalline, bonded double-SOI accumulation modulator has been presented [22], however the authors state that the device speed can be increased by a factor of 2.4, and the power consumption decreased by a factor of 2, by eliminating the parasitic capacitance between the top and bottom SOI in the non-active region.

Several results have been presented of high-speed (up to 56Gb/s [23]) reverse biased pin-diode injection modulators which utilize doped periodic fin electrical contacts perpendicular to the central strip waveguide [23–27]. One major benefit of using periodic fin electrical contacts as opposed to a thin SOI planar contact (common in conventional strip/rib waveguides) is the ability to dry etch completely to the stopping BOX layer instead of relying on partial etching through the SOI layer with no well defined stopping layer, which leads to local and macro-scale fabrication variations and reduces overall yield. Fin parameters can be optimized as per the device requirements, with narrow fins exhibiting lower optical loss at the cost of higher resistance (therefore higher V_πL), and vice versa for wide fins.

The key challenge associated with developing a fully-crystalline, horizontal slot, low V_πL accumulation modulator is the problem of how to pattern the bottom SOI of a double-SOI substrate post-bonding (patterning cannot be done pre-bonding, as this would lead to intolerable surface contaminations/defects/imperfections which would seriously degrade the horizontal gate oxide bonding quality), to achieve a fully-crystalline version of the a-Si horizontal slot accumulation modulator. If the bottom SOI is not removed, this leads to parasitic capacitance (increasing power consumption) and restricts the device architecture to microdisk or microring resonators, as the active region cannot accommodate a waveguide required for MZI phase shifters. In this work we propose and demonstrate a new fabrication technique which involves anisotropic wet etching of mirror aligned top and bottom SOI planes which for the first time successfully overcomes this key challenge. We demonstrate the feasibility of this technique by fabricating and characterizing fully passive, undoped, fin waveguide devices and fin waveguide MZI devices. The paper is organized as follows. In Section 2, we introduce and discuss the new device design and the figures of merit achievable according to simulation. In Section 3.1, we outline the new fabrication process required to realize the new device design, and outline the fabrication plan. In Section 3.2, we detail the fabrication of bonded metal-oxide-semiconductor (MOS) capacitor devices (to characterise bonding quality) and in section 3.3 we detail the successful fabrication of anisotropically wet etched passive fin-waveguides on bonded double-SOI. In Section 4 we present and discuss the characterisation results of the devices (MOS capacitor, strip/fin-waveguides, passive MZIs) outlined in Section 3.