Memristors prompted an increasing interest among the neuromorphic community since these devices were successfully demonstrated in HP labs. Since then, there have been a number of memristive devices developed based on diverse materials and technologies. Among others, Oxide-based Random-Access Memory (OxRAM) structures are one of the most promising approaches to implement synaptic elements in neuromorphic computing systems, because of their low-switching energy and high endurance.

Although OxRAMs have also been demonstrated to operate as analog memories, here we focus on their exploitation as binary (1-bit) memory cells. The OxRAM devices to be used in this work are optimized for binary memory applications. This binary OxRAM (as highlighted in Fig. 1) has to be first formed and then switched between two states: SET or Low Resistance State (LRS)– typically in the order of kΩ – and RESET or High Resistance State (HRS)– in the order of few hundreds of kΩ to MΩ. The resistance states are chosen by applying a control voltage to a selector MOSFET connected in series with the OxRAM in order to avoid sneak path currents, giving rise to a device often referred to as 1T1R, as shown in Fig. 1. In order to form the filament of the OxRAM, the selector MOSFET is biased with a high positive voltage (≈4V) at the top terminal, the bottom terminal is biased with 0V and the gate terminal voltage (1.5 V to 2.5 V) is adjusted such that the recommended compliance forming current of about 1μA is set. For a RESET operation, the top terminal is biased with 0V, the bottom terminal is biased with a positive voltage (≈4V) and the gate terminal is kept fully ON. For a SET operation the top terminal is biased with a positive voltage (≈2V), the bottom terminal is biased with 0V and the gate is set to limit the current to about 100μA. For a READ operation, the top terminal is biased with a small positive voltage (0.2 or 0.3V), the bottom terminal is biased with 0V and the gate is kept fully ON.

Fig. 1. 1T1R memristive synapse structure

Here we consider a memristor-based fully connected feed-forward neural network, which mainly comprises the pre-synaptic neurons, the memristive crossbar and the post-synaptic neurons. As the LRS current across a crossbar line is high due to the typical low resistance during an inference read operation (after a SET operation), an extremely large integrating capacitor would be needed (larger than nFs) at the post-synaptic neuron for reasonable integration speed, making IC integration impossible. Hence, a current attenuator is needed to scale down the read current.

Several current attenuating strategies exist such as the Gilbert’s current normalizer circuit, MOS-ladder and the Winner Take All (WTA) based current attenuator. This paper considers Gilbert’s current normalizer circuit as reference, on which modifications are done to ease attenuation of an inference current. The idea is based on creating a splitting of the inference current by a factor of about two by using a MOS biased in ohmic region. This paper proposes a Modified Current Normalizer (MCN) circuit for attenuating a crossbar read-out line current. Simulation results taking into account the effect of PVT variations are shown to validate the proposed circuit technique.

Fig.2. Scheme of a 4 × 4 1T1R crossbar with pre-synaptic neurons, current attenuators and post-synaptic neurons.