Recent advances in self-powered systems have ushered a new revolution for ICT systems. The technology push towards designing batteryless and long-life ubiquitous systems, in their trillions, has never been so strong. This has been matched by equally powerful application pull for creating myriad of new pervasive electronic objects that can autonomously function, ensuring safety and reliability. Without a doubt, these objects will be at the very core of our everyday life, like guardian angels looking after our health, monitoring and controlling our homes, offices, cars and cities. However, designing reliable electronics is a daunting challenge. It is a genuine concern for low-power, nanoscale systems operating in harsh environments. The device geometry is typically so small that even the slightest perturbation (such as particle radiation) can alter the electrical properties, and as such inflict logic flips or faults in the system. The traditional approaches to addressing this is to incorporate additional circuits for fault detection and tolerance, which can incur energy and cost overheads. This can exacerbate further when the number of faults continues to increase in extremely harsh environments. Unfortunately, minuscule energy harvesters, which are replacing traditional batteries for autonomy and long-life considerations, are exacerbating this challenge further. These harvesters transduce electrical energy from the physical energy, e.g. vibration, thermal, solar and/or kinetic energy, with two major limitations. Firstly, the energy scavenged is generally very limited; energy storage is often not feasible due to size and weight restrictions of supercapacitors. Secondly, the harvested energy varies over time unpredictably depending on the environment. Computing under such variable and limited power supplies, while also ensuring safety and reliability requires a thoroughgoing design thinking - perhaps more appropriately a paradigm shift. How can we design new breed of electronics that can reliably compute on nanoscale circuits at zero cost under unreliable power supplies? This postgraduate research project will investigate a new circuit design approach in addressing the above question. The aim will be to instill the following two unique properties in electronic circuits, disrupting the existing circuit design methods. Power and logic resilience is the first property in the presence of energy variations and/or induced charges, which will require circuits to operate reliably over a dynamic energy envelope. This is a step change from the traditional digital circuits that operate in discrete voltage/frequency modes near- or above-threshold operating points, governed by the power delivery subsystem . Underpinning our existing works, the research will primarily target designing mixed signal (i.e. analogue/digital) circuit components using the principle of temporal computing. By designing circuits in this mode, the supply voltages and frequencies can be flexibly varied and stretched beyond the norm by two orders of magnitude or more. To enable survival under power cuts, each circuit node will incorporate non-volatile registers (using memristors). Further, spatial data representations will be replaced by duty cycle of clock signals fed into a network of inverter cells, which can drastically cut down the complexity of arithmetic logic processing and data movement at analogue accuracy. Our previous studies have established that circuits designed using temporal methods have significantly higher tolerance to induced charges, as periodic pulses in clock signals can refresh logic flips. This will be further reinforced by practical design and implementation. Power-compute co-design is the second property, which will couple power scheduling decisions to available power/energy levels by suitably selecting the circuit for delivering on the required compute functionality.